TTBR1_EL2

When HCR_EL2.E2H is 1, holds the base address of the translation table for the initial lookup for stage 1 of the translation of an address from the higher VA range in the EL2&0 translation regime, and other information for this translation regime.

Configuration

This register is present only when FEAT_VHE is implemented. Otherwise, direct accesses to TTBR1_EL2 are UNDEFINED.

This register has no effect if EL2 is not enabled in the current Security state.

TTBR1_EL2 is a 128-bit register that can also be accessed as a 64-bit value. If it is accessed as a 64-bit register, accesses read and write bits [63:0] and do not modify bits [127:64].

Attributes

Field descriptions

When FEAT_D128 is implemented, TCR2_EL2.D128 == 1 and HCR_EL2.E2H == 1:

Bits [127:88]

BADDR, bits [87:80, 47:5]

Bits [79:64]

ASID, bits [63:48]

Bits [4:3]

SKL, bits [2:1]

SKL	Meaning
0b00	Skip 0 level from the regular start level.
0b01	Skip 1 level from the regular start level.
0b10	Skip 2 levels from the regular start level.
0b11	Skip 3 levels from the regular start level.

CnP, bit [0]
When FEAT_TTCNP is implemented:

Common not Private. This bit indicates whether each entry that is pointed to by TBR1_EL2 is a member of a common set that can be used by every PE in the Inner Shareable domain for which the value of TTBR1_EL2.CnP is 1.

CnP	Meaning
0b0	The translation table entries pointed to by TTBR1_EL2 for the current ASID are permitted to differ from corresponding entries for TTBR1_EL2 for other PEs in the Inner Shareable domain. This is not affected by: The value of TTBR1_EL2.CnP on those other PEs. The value of the current ASID.
0b1	The translation table entries pointed to by TTBR1_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR1_EL2.CnP is 1 and all of the following apply: The translation table entries are pointed to by TTBR1_EL2. The ASID is the same as the current ASID.

CnP

Meaning

0b0

The translation table entries pointed to by TTBR1_EL2 for the current ASID are permitted to differ from corresponding entries for TTBR1_EL2 for other PEs in the Inner Shareable domain. This is not affected by:

The value of TTBR1_EL2.CnP on those other PEs.
The value of the current ASID.

0b1

The translation table entries pointed to by TTBR1_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR1_EL2.CnP is 1 and all of the following apply:

The translation table entries are pointed to by TTBR1_EL2.
The ASID is the same as the current ASID.

This bit is permitted to be cached in a TLB.

Note

TTBR1_EL2 is accessible only when the value of HCR_EL2.E2H is 1, meaning the current translation regime is the EL2&0 regime.
If the value of the TTBR1_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR1_EL2s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

When FEAT_D128 is not implemented or TCR2_EL2.D128 == 0:

ASID, bits [63:48]

BADDR[47:1], bits [47:1]

Translation table base address:

Bits A[47:x] of the stage 1 translation table base address bits are in register bits[47:x].
Bits A[(x-1):0] of the stage 1 translation table base address are zero.

Address bit x is the minimum address bit required to align the translation table to the size of the table. The AArch64 Virtual Memory System Architecture chapter describes how x is calculated based on the value of TCR_EL2.T1SZ, the translation stage, and the translation granule size.

Note

If an OA size of more than 48 bits is in use, and the translation table has fewer than eight entries, the table must be aligned to 64 bytes. Otherwise the translation table must be aligned to the size of the table.

If the value of TCR_EL2.{I}PS is not 0b110, then:

Register bits[(x-1):1] are RES0.
If the implementation supports 52-bit PAs and IPAs, then bits A[51:48] of the stage 1 translation table base address are 0b0000.

If FEAT_LPA is implemented and the value of TCR_EL2.{I}PS is 0b110, then:

Bits A[51:48] of the stage 1 translation table base address bits are in register bits[5:2].
Register bit[1] is RES0.
The smallest permitted value of x is 6.
When x>6, register bits[(x-1):6] are RES0.

Note

The OA size specified by TCR_EL2.{I}PS is determined as follows:

The value of TCR_EL2.PS when the value of HCR_EL2.E2H is 0.
The value of TCR_EL2.IPS when the value of HCR_EL2.E2H is 1.

TCR_EL2.{I}PS==0b110 is permitted when:

FEAT_LPA is implemented and the 64KB translation granule is used.
FEAT_LPA2 is implemented and the 4KB or 16KB translation granule is used.

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation does not support a 52 bit PA size, if a translation table lookup uses this register when the Effective value of TCR_EL2.{I}PS is 0b110 and the value of register bits[5:2] is nonzero, an Address size fault is generated.

When the value of ID_AA64MMFR0_EL1.PARange indicates that the implementation supports a 56 bit PA size, bits A[55:52] of the stage 1 translation table base address are zero.

If any register bit[47:1] that is defined as RES0 has the value 1 when a translation table walk is done using TTBR1_EL2, then the translation table base address might be misaligned, with effects that are CONSTRAINED UNPREDICTABLE, and must be one of the following:

Bits A[(x-1):0] of the stage 1 translation table base address are treated as if all the bits are zero. The value read back from the corresponding register bits is either the value written to the register or zero.
The result of the calculation of an address for a translation table walk using this register can be corrupted in those bits that are nonzero.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

CnP, bit [0]
When FEAT_TTCNP is implemented:

CnP	Meaning
0b0	The translation table entries pointed to by TTBR1_EL2 for the current ASID are permitted to differ from corresponding entries for TTBR1_EL2 for other PEs in the Inner Shareable domain. This is not affected by: The value of TTBR1_EL2.CnP on those other PEs. The value of the current ASID.
0b1	The translation table entries pointed to by TTBR1_EL2 are the same as the translation table entries for every other PE in the Inner Shareable domain for which the value of TTBR1_EL2.CnP is 1 and all of the following apply: The translation table entries are pointed to by TTBR1_EL2. The ASID is the same as the current ASID.

CnP

Meaning

0b0

The value of TTBR1_EL2.CnP on those other PEs.
The value of the current ASID.

0b1

The translation table entries are pointed to by TTBR1_EL2.
The ASID is the same as the current ASID.

This bit is permitted to be cached in a TLB.

Note

TTBR1_EL2 is accessible only when the value of HCR_EL2.E2H is 1, meaning the current translation regime is the EL2&0 regime.
If the value of the TTBR1_EL2.CnP bit is 1 on multiple PEs in the same Inner Shareable domain and those TTBR1_EL2s do not point to the same translation table entries when the other conditions specified for the case when the value of CnP is 1 apply, then the results of translations are CONSTRAINED UNPREDICTABLE, see 'CONSTRAINED UNPREDICTABLE behaviors due to caching of control or data values'.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Otherwise:

Accessing TTBR1_EL2

When HCR_EL2.E2H is 1, without explicit synchronization, access from EL2 using the mnemonic TTBR1_EL2 or TTBR1_EL1 are not guaranteed to be ordered with respect to accesses using the other mnemonic.

Accesses to this register use the following encodings in the System register encoding space:

MRS <Xt>, TTBR1_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then X[t, 64] = TTBR1_EL2<63:0>; elsif PSTATE.EL == EL3 then X[t, 64] = TTBR1_EL2<63:0>;

MSR TTBR1_EL2, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x18); else UNDEFINED; elsif PSTATE.EL == EL2 then TTBR1_EL2<63:0> = X[t, 64]; elsif PSTATE.EL == EL3 then TTBR1_EL2<63:0> = X[t, 64];

MRS <Xt>, TTBR1_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then X[t, 64] = NVMem[0x210]; else X[t, 64] = TTBR1_EL1<63:0>; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then X[t, 64] = TTBR1_EL2<63:0>; else X[t, 64] = TTBR1_EL1<63:0>; elsif PSTATE.EL == EL3 then X[t, 64] = TTBR1_EL1<63:0>;

MSR TTBR1_EL1, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x18); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x210] = X[t, 64]; else TTBR1_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL2 then if HCR_EL2.E2H == '1' then TTBR1_EL2<63:0> = X[t, 64]; else TTBR1_EL1<63:0> = X[t, 64]; elsif PSTATE.EL == EL3 then TTBR1_EL1<63:0> = X[t, 64];

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR1_EL2

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else (X[t + 1, 64], X[t, 64]) = Split(TTBR1_EL2, 64); elsif PSTATE.EL == EL3 then (X[t + 1, 64], X[t, 64]) = Split(TTBR1_EL2, 64);

When FEAT_D128 is implemented
MSRR TTBR1_EL2, <Xt+1>, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b100	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if EL2Enabled() && HCR_EL2.NV == '1' then AArch64.SystemAccessTrap(EL2, 0x14); else UNDEFINED; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); else TTBR1_EL2<127:0> = X[t + 1, 64]:X[t, 64]; elsif PSTATE.EL == EL3 then TTBR1_EL2<127:0> = X[t + 1, 64]:X[t, 64];

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR1_EL1

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TRVM == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGRTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.D128En == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then (X[t + 1, 64], X[t, 64]) = Split(NVMem[0x210, 128], 64); else (X[t + 1, 64], X[t, 64]) = Split(TTBR1_EL1, 64); elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HCR_EL2.E2H == '1' then (X[t + 1, 64], X[t, 64]) = Split(TTBR1_EL2, 64); else (X[t + 1, 64], X[t, 64]) = Split(TTBR1_EL1, 64); elsif PSTATE.EL == EL3 then (X[t + 1, 64], X[t, 64]) = Split(TTBR1_EL1, 64);

When FEAT_D128 is implemented
MSRR TTBR1_EL1, <Xt+1>, <Xt>

op0	op1	CRn	CRm	op2
0b11	0b000	0b0010	0b0000	0b001

if PSTATE.EL == EL0 then UNDEFINED; elsif PSTATE.EL == EL1 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif EL2Enabled() && HCR_EL2.TVM == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && IsFeatureImplemented(FEAT_FGT) && (!HaveEL(EL3) || SCR_EL3.FGTEn == '1') && HFGWTR_EL2.TTBR1_EL1 == '1' then AArch64.SystemAccessTrap(EL2, 0x14); elsif EL2Enabled() && (!IsHCRXEL2Enabled() || HCRX_EL2.D128En == '0') then AArch64.SystemAccessTrap(EL2, 0x14); elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif EL2Enabled() && HCR_EL2.<NV2,NV1,NV> == '111' then NVMem[0x210, 128] = X[t + 1, 64]:X[t, 64]; else TTBR1_EL1<127:0> = X[t + 1, 64]:X[t, 64]; elsif PSTATE.EL == EL2 then if Halted() && HaveEL(EL3) && EDSCR.SDD == '1' && boolean IMPLEMENTATION_DEFINED "EL3 trap priority when SDD == '1'" && SCR_EL3.D128En == '0' then UNDEFINED; elsif HaveEL(EL3) && SCR_EL3.D128En == '0' then if Halted() && EDSCR.SDD == '1' then UNDEFINED; else AArch64.SystemAccessTrap(EL3, 0x14); elsif HCR_EL2.E2H == '1' then TTBR1_EL2<127:0> = X[t + 1, 64]:X[t, 64]; else TTBR1_EL1<127:0> = X[t + 1, 64]:X[t, 64]; elsif PSTATE.EL == EL3 then TTBR1_EL1<127:0> = X[t + 1, 64]:X[t, 64];

127	126	125	124	123	122	121	120	119	118	117	116	115	114	113	112	111	110	109	108	107	106	105	104	103	102	101	100	99	98	97	96
RES0
95	94	93	92	91	90	89	88	87	86	85	84	83	82	81	80	79	78	77	76	75	74	73	72	71	70	69	68	67	66	65	64
RES0								BADDR[50:43]								RES0
63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
ASID																BADDR[42:0]
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BADDR[42:0]																											RES0		SKL		CnP

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ASID																BADDR[47:1]
BADDR[47:1]																															CnP

TTBR1_EL2, Translation Table Base Register 1 (EL2)

Purpose

Configuration

Attributes

Field descriptions

When FEAT_D128 is implemented, TCR2_EL2.D128 == 1 and HCR_EL2.E2H == 1:

Bits [127:88]

BADDR, bits [87:80, 47:5]

Bits [79:64]

ASID, bits [63:48]

Bits [4:3]

SKL, bits [2:1]

CnP, bit [0]
When FEAT_TTCNP is implemented:

Otherwise:

When FEAT_D128 is not implemented or TCR2_EL2.D128 == 0:

ASID, bits [63:48]

BADDR[47:1], bits [47:1]

CnP, bit [0]
When FEAT_TTCNP is implemented:

Otherwise:

Accessing TTBR1_EL2

MRS <Xt>, TTBR1_EL2

MSR TTBR1_EL2, <Xt>

MRS <Xt>, TTBR1_EL1

MSR TTBR1_EL1, <Xt>

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR1_EL2

When FEAT_D128 is implemented
MSRR TTBR1_EL2, <Xt+1>, <Xt>

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR1_EL1

When FEAT_D128 is implemented
MSRR TTBR1_EL1, <Xt+1>, <Xt>

TTBR1_EL2, Translation Table Base Register 1 (EL2)

Purpose

Configuration

Attributes

Field descriptions

When FEAT_D128 is implemented, TCR2_EL2.D128 == 1 and HCR_EL2.E2H == 1:

Bits [127:88]

BADDR, bits [87:80, 47:5]

Bits [79:64]

ASID, bits [63:48]

Bits [4:3]

SKL, bits [2:1]

CnP, bit [0]When FEAT_TTCNP is implemented:

Otherwise:

When FEAT_D128 is not implemented or TCR2_EL2.D128 == 0:

ASID, bits [63:48]

BADDR[47:1], bits [47:1]

CnP, bit [0]When FEAT_TTCNP is implemented:

Otherwise:

Accessing TTBR1_EL2

MRS <Xt>, TTBR1_EL2

MSR TTBR1_EL2, <Xt>

MRS <Xt>, TTBR1_EL1

MSR TTBR1_EL1, <Xt>

When FEAT_D128 is implemented MRRS <Xt+1>, <Xt>, TTBR1_EL2

When FEAT_D128 is implemented MSRR TTBR1_EL2, <Xt+1>, <Xt>

When FEAT_D128 is implemented MRRS <Xt+1>, <Xt>, TTBR1_EL1

When FEAT_D128 is implemented MSRR TTBR1_EL1, <Xt+1>, <Xt>

CnP, bit [0]
When FEAT_TTCNP is implemented:

CnP, bit [0]
When FEAT_TTCNP is implemented:

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR1_EL2

When FEAT_D128 is implemented
MSRR TTBR1_EL2, <Xt+1>, <Xt>

When FEAT_D128 is implemented
MRRS <Xt+1>, <Xt>, TTBR1_EL1

When FEAT_D128 is implemented
MSRR TTBR1_EL1, <Xt+1>, <Xt>