The CNTVOFF characteristics are:
Holds the 64-bit virtual offset for a CNTBaseN frame that has virtual timer capability. This is the offset between real time and virtual time.
It is IMPLEMENTATION DEFINED whether CNTVOFF is implemented in the Core power domain or in the Debug power domain.
For more information, see 'Power and reset domains for the system level implementation of the Generic Timer'.
CNTVOFF is a 64-bit register.
63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Virtual offset | |||||||||||||||||||||||||||||||
Virtual offset |
Virtual offset.
The reset behavior of this field is:
CNTVOFF is implemented, as a RO register, in any implemented CNTBaseN frame that has virtual timer capability.
'CNTCTLBase status and control fields for the CNTBaseN and CNTEL0BaseN frames' describes the status fields that identify whether a CNTBaseN frame is implemented, and for an implemented frame:
For an implemented CNTBaseN frame that has virtual timer capability:
CNTVOFF is never visible in any CNTEL0BaseN frame. This means that the CNTVOFF address in any implemented CNTEL0BaseN frame is RAZ/WI.
In an implementation that supports 64-bit atomic accesses, a CNTVOFF{<n>} register must be accessible as an atomic 64-bit value.
Component | Frame | Offset | Range |
---|---|---|---|
Timer | CNTBaseN | 0x018 | 31:0 |
Accesses on this interface are RO.
Component | Frame | Offset | Range |
---|---|---|---|
Timer | CNTBaseN | 0x01C | 63:32 |
Accesses on this interface are RO.
04/07/2023 11:22; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.