The GICR_VSGIR characteristics are:
Requests the pending state of virtual SGIs for a specified vPE.
This register is present only when FEAT_GICv4p1 is implemented. Otherwise, direct accesses to GICR_VSGIR are RES0.
A copy of this register is provided for each Redistributor.
GICR_VSGIR is a 32-bit register.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | vPEID | ||||||||||||||||||||||||||||||
Reserved, RES0.
ID of target vPE
Writing this field is CONSTRAINED UNPREDICTABLE when GICR_VSGIPENDR.Busy == 1, with either the write ignored or a new query started.
Writing a value greater than the configured vPEID width behaviur is CONSTRAINED UNPREDICTABLE, with either:
vPEID is treated as having an UNKNOWN valid value.
The write is ignored.
The size of this field is IMPLEMENTATION DEFINED, and is specified by the GICD_TYPER2.VIL and GICD_TYPER2.VID fields. Unimplemented bits are RES0.
| Component | Frame | Offset | Instance |
|---|---|---|---|
| GIC Redistributor | VLPI_base | 0x0080 | GICR_VSGIR |
Accesses on this interface are WO.
04/07/2023 11:26; 1b994cb0b8c6d1ae5a9a15edbc8bd6ce3b5c7d68
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