GITS_TYPER

ITS cache invalidation behavior on disable.

INV	Meaning
0b0	It is IMPLEMENTATION DEFINED whether ITS caches are invalidated on clearing GITS_CTLR.Enabled and GITS_BASER<n>.Valid.
0b1	ITS caches are invalidated on clearing GITS_CTLR.Enabled and GITS_BASER<n>.Valid.

If GITS_TYPER.INV is 1, after the following sequence:

GITS_CTLR.Enabled written to 0.
A read of GITS_CTLR.Quiescent returns 1.
GITS_BASER<n>.Valid written to 0.

There is no cached information from the ITS memory structure pointed to by GITS_BASER<n>.

UMSIirq, bit [45]

Indicates support for generating an interrupt on receiving unmapped MSI.

UMSIirq	Meaning
0b0	Interrupt on unmapped MSI not supported.
0b1	Interrupt on unmapped MSI is supported.

If GITS_TYPER.UMSI is 0, this field is RES0.

UMSI, bit [44]

Indicates suport for reporting receipt of unmapped MSIs.

UMSI	Meaning
0b0	Reporting of unmapped MSIs is not supported.
0b1	Reporting of unmapped MSIs is supported.

nID, bit [43]
When FEAT_GICv4p1 is implemented:

nID

nID	Meaning
0b0	Individual doorbell interrupt supported.
0b1	Individual doorbell interrupt not supported.

Otherwise:

SVPET, bits [42:41]
When FEAT_GICv4p1 is implemented:

SVPET

SVPET	Meaning
0b00	vPE Table is not shared with Redistributors.
0b01	vPE Table is shared with the groups of Redistributors indicated by GITS_MPIDR.Aff3.
0b10	vPE Table is shared with the groups of Redistributors indicated by GITS_MPIDR fields Aff3 and Aff2.
0b11	vPE Table is shared with the groups of Redistributors indicated by GITS_MPIDR fields Aff3, Aff2 and Aff1.

Otherwise:

VMAPP, bit [40]
When FEAT_GICv4p1 is implemented:

VMAPP

VMAPP	Meaning
0b0	FEAT_GICv4 VMAPP command layout.
0b1	FEAT_GICv4p1 VMAPP command layout.

Otherwise:

VSGI, bit [39]
When FEAT_GICv4p1 is implemented:

VSGI

VSGI	Meaning
0b0	Direct injection of SGIs is not supported.
0b1	Direct injection of SGIs is supported.

Otherwise:

MPAM, bit [38]
When FEAT_GICv3p1 is implemented:

MPAM

MPAM	Meaning
0b0	MPAM is not supported.
0b1	MPAM is supported.

Otherwise:

VMOVP, bit [37]

Indicates the form of the VMOVP command.

VMOVP	Meaning
0b0	When moving a vPE, software must issue a VMOVP on all ITSs that have mappings for that vPE. The ITSList and Sequence Number fields in the VMOVP command must ensure synchronization, otherwise behavior is UNPREDICTABLE.
0b1	When moving a vPE, software must only issue a VMOVP on one of the ITSs that has a mapping for that vPE. The ITSList and Sequence Number fields in the VMOVP command are RES0.

CIL, bit [36]

Collection ID Limit.

CIL	Meaning
0b0	ITS supports 16-bit Collection ID, GITS_TYPER.CIDbits is RES0.
0b1	GITS_TYPER.CIDbits indicates supported Collection ID size

In implementations that do not support Collections in external memory, this bit is RES0 and the number of Collections supported is reported by GITS_TYPER.HCC.

CIDbits, bits [35:32]

Number of Collection ID bits.

The number of bits of Collection ID minus one.
When GITS_TYPER.CIL == 0, this field is RES0.

HCC, bits [31:24]

Hardware Collection Count. The number of interrupt collections supported by the ITS without provisioning of external memory.

Note

Collections held in hardware are unmapped at reset.

Bits [23:20]

PTA, bit [19]

Physical Target Addresses. Indicates the format of the target address:

PTA	Meaning
0b0	The target address corresponds to the PE number specified by GICR_TYPER.Processor_Number.
0b1	The target address corresponds to the base physical address of the required Redistributor.

For more information, see 'RDbase' in ARM® Generic Interrupt Controller Architecture Specification, GIC architecture version 3.0 and version 4.0 (ARM IHI 0069).

SEIS, bit [18]

SEI support. Indicates whether the virtual CPU interface supports generation of SEIs:

SEIS	Meaning
0b0	The ITS does not support local generation of SEIs.
0b1	The ITS supports local generation of SEIs.

Devbits, bits [17:13]

The number of DeviceID bits implemented, minus one.

ID_bits, bits [12:8]

The number of EventID bits implemented, minus one.

ITT_entry_size, bits [7:4]

Read-only. Indicates the number of bytes per translation table entry, minus one.

For more information about the ITS command 'MAPD', see MAPD.

IMPLEMENTATION DEFINED, bit [3]

IMPLEMENTATION DEFINED.

CCT, bit [2]

Cumulative Collection Tables.

CCT	Meaning
0b0	The total number of supported collections is determined by the number of collections held in memory only.
0b1	The total number of supported collections is determined by number of collections that are held in memory and the number indicated by GITS_TYPER.HCC.

If GITS_TYPER.HCC == 0, or if memory backed collections are not supported (all GITS_BASER<n>.Type != 100), this bit is RES0.

Virtual, bit [1]
When FEAT_GICv4 is implemented:

Indicates whether the ITS supports virtual LPIs and direct injection of virtual LPIs:

Virtual	Meaning
0b0	The ITS does not support virtual LPIs or direct injection of virtual LPIs.
0b1	The ITS supports virtual LPIs and direct injection of virtual LPIs.

Otherwise:

Physical, bit [0]

Indicates whether the ITS supports physical LPIs:

Physical	Meaning
0b0	The ITS does not support physical LPIs.
0b1	The ITS supports physical LPIs.

This field is RES1, indicating that the ITS supports physical LPIs.

Accessing GITS_TYPER

GITS_TYPER can be accessed through the memory-mapped interfaces:

GITS_TYPER, ITS Type Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:47]

INV, bit [46]

UMSIirq, bit [45]

UMSI, bit [44]

nID, bit [43]
When FEAT_GICv4p1 is implemented:

Otherwise:

SVPET, bits [42:41]
When FEAT_GICv4p1 is implemented:

Otherwise:

VMAPP, bit [40]
When FEAT_GICv4p1 is implemented:

Otherwise:

VSGI, bit [39]
When FEAT_GICv4p1 is implemented:

Otherwise:

MPAM, bit [38]
When FEAT_GICv3p1 is implemented:

Otherwise:

VMOVP, bit [37]

CIL, bit [36]

CIDbits, bits [35:32]

HCC, bits [31:24]

Bits [23:20]

PTA, bit [19]

SEIS, bit [18]

Devbits, bits [17:13]

ID_bits, bits [12:8]

ITT_entry_size, bits [7:4]

IMPLEMENTATION DEFINED, bit [3]

CCT, bit [2]

Virtual, bit [1]
When FEAT_GICv4 is implemented:

Otherwise:

Physical, bit [0]

Accessing GITS_TYPER

GITS_TYPER can be accessed through the memory-mapped interfaces:

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0																	INV	UMSIirq	UMSI	nID	SVPET		VMAPP	VSGI	MPAM	VMOVP	CIL	CIDbits
HCC								RES0				PTA	SEIS	Devbits					ID_bits					ITT_entry_size				IMPLEMENTATION DEFINED	CCT	Virtual	Physical

GITS_TYPER, ITS Type Register

Purpose

Configuration

Attributes

Field descriptions

Bits [63:47]

INV, bit [46]

UMSIirq, bit [45]

UMSI, bit [44]

nID, bit [43]When FEAT_GICv4p1 is implemented:

Otherwise:

SVPET, bits [42:41]When FEAT_GICv4p1 is implemented:

Otherwise:

VMAPP, bit [40]When FEAT_GICv4p1 is implemented:

Otherwise:

VSGI, bit [39]When FEAT_GICv4p1 is implemented:

Otherwise:

MPAM, bit [38]When FEAT_GICv3p1 is implemented:

Otherwise:

VMOVP, bit [37]

CIL, bit [36]

CIDbits, bits [35:32]

HCC, bits [31:24]

Bits [23:20]

PTA, bit [19]

SEIS, bit [18]

Devbits, bits [17:13]

ID_bits, bits [12:8]

ITT_entry_size, bits [7:4]

IMPLEMENTATION DEFINED, bit [3]

CCT, bit [2]

Virtual, bit [1]When FEAT_GICv4 is implemented:

Otherwise:

Physical, bit [0]

Accessing GITS_TYPER

GITS_TYPER can be accessed through the memory-mapped interfaces:

nID, bit [43]
When FEAT_GICv4p1 is implemented:

SVPET, bits [42:41]
When FEAT_GICv4p1 is implemented:

VMAPP, bit [40]
When FEAT_GICv4p1 is implemented:

VSGI, bit [39]
When FEAT_GICv4p1 is implemented:

MPAM, bit [38]
When FEAT_GICv3p1 is implemented:

Virtual, bit [1]
When FEAT_GICv4 is implemented: