TCR2_EL2

Reserved, RES0.

This field controls the enabling of the Alternate MECID translations for the EL2 translation regime.

TCR2_EL2.AMEC0 is provided to enable the safe update of MECID_A0_EL2, by disabling access and speculation to AMEC==1 Block or Page descriptors during the update.

AMEC0	Meaning
0b0	Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.
0b1	Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A0_EL2.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When IsCurrentSecurityState(SS_Secure), access to this field is RES0.
When IsCurrentSecurityState(SS_NonSecure), access to this field is RES0.

Reserved, RES0.

Hardware managed Access Flag for Table descriptors.

Enables the Hardware managed Access Flag for Table descriptors.

HAFT	Meaning
0b0	Hardware managed Access Flag for Table descriptors is disabled.
0b1	Hardware managed Access Flag for Table descriptors is enabled.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Permit Translation table walk Incoherence.

Permits RCWS instructions to generate writes that have the Reduced Coherence property.

PTTWI	Meaning
0b0	Write accesses generated by RCWS at EL2 or EL2&0 do not have the Reduced Coherence property.
0b1	Write accesses generated by RCWS at EL2 or EL2&0 have the Reduced Coherence property.

This bit is permitted to be implemented as a read-only bit with a fixed value of 0.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Enable Attribute Indexing Extension. Control for Attribute Indexing Extension for stage 1 EL2 translation.

AIE	Meaning
0b0	Attribute Indexing Extension Disabled.
0b1	Attribute Indexing Extension Enabled.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

POE. Controls setting of permission overlay for EL2 accesses in stage 1 of the EL2 translation regime.

POE	Meaning
0b0	Permission overlay disabled for EL2 access in stage 1 of EL2 translation regime.
0b1	Permission overlay enabled for EL2 access in stage 1 of EL2 translation regime.

This bit is not permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Select Permission Model. Controls setting of indirect permission model in stage 1 EL2 translation.

PIE	Meaning
0b0	Direct permission model.
0b1	Indirect permission model.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Protected attribute enable.Indicates use of bit[52] of the stage 1 translation table entry.

PnCH	Meaning
0b0	Bit[52] of each stage 1 translation table entry does not indicate protected attribute.
0b1	Bit[52] of each stage 1 translation table entry indicates protected attribute.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Disable the Contiguous bit for the Start Table for TTBR1_EL2.

DisCH1	Meaning
0b0	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL2 is not affected by this field.
0b1	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR1_EL2 is treated as 0.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Disable the Contiguous bit for the Start Table for TTBR0_EL2.

DisCH0	Meaning
0b0	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL2 is not affected by this field.
0b1	The Contiguous bit of Block or Page descriptors of the Start Table for TTBR0_EL2 is treated as 0.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

This field controls the enabling of the Alternate MECID translations for accesses in the TTBR1_EL2 half of the VA range, for the EL2&0 translation regime.

TCR2_EL2.AMEC1 is provided to enable the safe update of MECID_A1_EL2, by disabling access and speculation to AMEC == 1 Block or Page descriptors during the update.

AMEC1	Meaning
0b0	Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.
0b1	Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A1_EL2.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When IsCurrentSecurityState(SS_Secure), access to this field is RES0.
When IsCurrentSecurityState(SS_NonSecure), access to this field is RES0.

Reserved, RES0.

This field controls the enabling of the Alternate MECID translations for accesses in the TTBR0_EL2 half of the VA range, for the EL2&0 translation regime.

TCR2_EL2.AMEC0 is provided to enable the safe update of MECID_A0_EL2, by disabling access and speculation to AMEC==1 Block or Page descriptors during the update.

AMEC0	Meaning
0b0	Use of a Block or Page descriptor containing AMEC == 1 generates a Translation fault.
0b1	Accesses translated by a Block or Page descriptor containing AMEC == 1 are associated with the MECID configured in MECID_A0_EL2.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

When SCTLR2_EL2.EMEC is 0, this field is ignored by the PE and the bit position of AMEC is RES0 in Block and Page descriptors.

The reset behavior of this field is:

On a Warm reset, this field resets to an architecturally UNKNOWN value.

Accessing this field has the following behavior:

When IsCurrentSecurityState(SS_Secure), access to this field is RES0.
When IsCurrentSecurityState(SS_NonSecure), access to this field is RES0.

Reserved, RES0.

Hardware managed Access Flag for Table descriptors.

Enables the Hardware managed Access Flag for Table descriptors.

HAFT	Meaning
0b0	Hardware managed Access Flag for Table descriptors is disabled.
0b1	Hardware managed Access Flag for Table descriptors is enabled.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Permit Translation table walk Incoherence.

Permits RCWS instructions to generate writes that have the Reduced Coherence property.

PTTWI	Meaning
0b0	Write accesses generated by RCWS do not have the Reduced Coherence property.
0b1	Write accesses generated by RCWS have the Reduced Coherence property.

This bit is permitted to be implemented as a read-only bit with a fixed value of 0.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Skip Level associated with translation table walks using TTBR1_EL2.

This determines the number of levels to be skipped in the regular start level of the stage 1 EL2&0 translation table walks using TTBR1_EL2.

SKL1	Meaning
0b00	Skip 0 level in the regular start level.
0b01	Skip 1 level in the regular start level.
0b10	Skip 2 levels in the regular start level.
0b11	Skip 3 levels in the regular start level.

This field is IGNORED when TCR2_EL2.D128 is 0.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Skip Level associated with translation table walks using TTBR0_EL2.

This determines the number of levels to be skipped in the regular start level of the stage 1 EL2&0 translation table walks using TTBR0_EL2.

SKL0	Meaning
0b00	Skip 0 level in the regular start level.
0b01	Skip 1 level in the regular start level.
0b10	Skip 2 levels in the regular start level.
0b11	Skip 3 levels in the regular start level.

This field is IGNORED when TCR2_EL2.D128 is 0.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Enables VMSAv9-128 translation system for stage 1 EL2&0 translation.

D128	Meaning
0b0	Translation system follows VMSA-64 translation process.
0b1	Translation system follows VMSAv9-128 translation process.

This field is IGNORED when TCR2_EL2.D128 is 0.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Enable Attribute Indexing Extension. Control for Attribute Indexing Extension for stage 1 EL2&0 translation.

AIE	Meaning
0b0	Attribute Indexing Extension Disabled.
0b1	Attribute Indexing Extension Enabled.

This field is RES1 when TCR2_EL2.D128 is 1.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

POE. Controls setting of permission overlay for EL2 accesses in stage 1 of the EL2&0 translation regime.

POE	Meaning
0b0	Permission overlay disabled for EL2 access in stage 1 of EL2&0 translation regime.
0b1	Permission overlay enabled for EL2 access in stage 1 of EL2&0 translation regime.

This bit is not permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

EL0 POE. controls setting of permission overlay in stage 1 of the EL2 translation regime.

E0POE	Meaning
0b0	Permission overlay disabled for EL0 access in stage 1 of EL2&0 translation regime.
0b1	Permission overlay enabled for EL0 access in stage 1 of EL2&0 translation regime.

This bit is not permitted to be cached in a TLB.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Select Permission Model. Controls setting of indirect permission model in stage 1 EL2 translation.

PIE	Meaning
0b0	Direct permission model.
0b1	Indirect permission model.

This field is RES1 when TCR2_EL2.D128 is 1.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

Protected attribute enable.Indicates use of bit[52] of the stage 1 translation table entry.

PnCH	Meaning
0b0	Bit[52] of each stage 1 translation table entry does not indicate protected attribute.
0b1	Bit[52] of each stage 1 translation table entry indicate protected attribute.

This field is RES1 when TCR2_EL2.D128 is 1.

This field is ignored by the PE and treated as zero when SCR_EL3.TCR2En == 0.

The reset behavior of this field is:

On a Warm reset:
- When the highest implemented Exception level is EL2, this field resets to 0.
- Otherwise, this field resets to an architecturally UNKNOWN value.

Reserved, RES0.

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																			AMEC0	HAFT	PTTWI	RES0					AIE	POE	RES0	PIE	PnCH

63	62	61	60	59	58	57	56	55	54	53	52	51	50	49	48	47	46	45	44	43	42	41	40	39	38	37	36	35	34	33	32
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RES0
RES0																DisCH1	DisCH0	AMEC1	AMEC0	HAFT	PTTWI	SKL1		SKL0		D128	AIE	POE	E0POE	PIE	PnCH

TCR2_EL2, Extended Translation Control Register (EL2)

Purpose

Configuration

Attributes

Field descriptions

When HCR_EL2.E2H == 0:

Bits [63:13]

AMEC0, bit [12]When FEAT_MEC is implemented:

Otherwise:

HAFT, bit [11]When FEAT_HAFT is implemented:

Otherwise:

PTTWI, bit [10]When FEAT_THE is implemented:

Otherwise:

Bits [9:5]

AIE, bit [4]When FEAT_AIE is implemented:

Otherwise:

POE, bit [3]When FEAT_S1POE is implemented:

Otherwise:

Bit [2]

PIE, bit [1]When FEAT_S1PIE is implemented:

Otherwise:

PnCH, bit [0]When FEAT_THE is implemented:

Otherwise:

When HCR_EL2.E2H == 1:

Bits [63:16]

DisCH1, bit [15]When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

Otherwise:

DisCH0, bit [14]When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

Otherwise:

AMEC1, bit [13]When FEAT_MEC is implemented:

Otherwise:

AMEC0, bit [12]When FEAT_MEC is implemented:

Otherwise:

HAFT, bit [11]When FEAT_HAFT is implemented:

Otherwise:

PTTWI, bit [10]When FEAT_THE is implemented:

Otherwise:

SKL1, bits [9:8]When FEAT_D128 is implemented:

Otherwise:

SKL0, bits [7:6]When FEAT_D128 is implemented:

Otherwise:

D128, bit [5]When FEAT_D128 is implemented:

Otherwise:

AIE, bit [4]When FEAT_AIE is implemented:

Otherwise:

POE, bit [3]When FEAT_S1POE is implemented:

Otherwise:

E0POE, bit [2]When FEAT_S1POE is implemented:

Otherwise:

PIE, bit [1]When FEAT_S1PIE is implemented:

Otherwise:

PnCH, bit [0]When FEAT_THE is implemented:

Otherwise:

Accessing TCR2_EL2

MRS <Xt>, TCR2_EL2

MSR TCR2_EL2, <Xt>

MRS <Xt>, TCR2_EL1

MSR TCR2_EL1, <Xt>

AMEC0, bit [12]
When FEAT_MEC is implemented:

HAFT, bit [11]
When FEAT_HAFT is implemented:

PTTWI, bit [10]
When FEAT_THE is implemented:

AIE, bit [4]
When FEAT_AIE is implemented:

POE, bit [3]
When FEAT_S1POE is implemented:

PIE, bit [1]
When FEAT_S1PIE is implemented:

PnCH, bit [0]
When FEAT_THE is implemented:

DisCH1, bit [15]
When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

DisCH0, bit [14]
When FEAT_D128 is implemented and TCR2_EL2.D128 == 1:

AMEC1, bit [13]
When FEAT_MEC is implemented:

AMEC0, bit [12]
When FEAT_MEC is implemented:

HAFT, bit [11]
When FEAT_HAFT is implemented:

PTTWI, bit [10]
When FEAT_THE is implemented:

SKL1, bits [9:8]
When FEAT_D128 is implemented:

SKL0, bits [7:6]
When FEAT_D128 is implemented:

D128, bit [5]
When FEAT_D128 is implemented:

AIE, bit [4]
When FEAT_AIE is implemented:

POE, bit [3]
When FEAT_S1POE is implemented:

E0POE, bit [2]
When FEAT_S1POE is implemented:

PIE, bit [1]
When FEAT_S1PIE is implemented:

PnCH, bit [0]
When FEAT_THE is implemented: